ECE 5720: Modeling and Synthesis of Digital Systems Using Verilog

Automatic design, synthesis, verification, and modeling of complex digital systems with Verilog are the main course objectives. Verilog for modeling existing circuits, as well as Verilog for design and automatic synthesis is discussed. Using Verilog for a design that consists of a hierarchy of components that include controllers, sequential and combinational parts is focused. Design description from transistor level to software interface will be discussed. Students will learn details of hardware of processor architectures and their peripherals. The course discusses module delay adjustments using Verilog path delay and distributed delay mechanisms. Testbench development and assertion verifications will be discussed. Students will learn to simulate verify, synthesize, and program their designs on an Altera development board using advanced Altera FPGAs.