ECE 5723: Methodologies for System Level Design and Modeling

This course discusses principles, methodologies and tools used for a modern hardware design process. Design flows and hardware languages needed for each stage of the design process are discussed. The use of transaction level modeling (TLM) for dealing with todays complex designs is emphasized. The course starts with a discussion of the evolution of hardware design methodologies, and then discusses the use of C++ for an algorithmic description of hardware. SystemC and its TLM derivative and the role of SystemC in high-level design will be discussed. In addition, RT level interfaces and the use of SystemC for this level of design will be covered. Timed, untimed, and approximately timed TLM models and modeling schemes will be presented. Use of TLM for fast design simulation, design space exploration, and high-level synthesis will be discussed. TLM testing methods and testing of TLM based NoCs will be discussed. The course starts with a complete design project and exercises various parts of this design as methodologies, concepts, and languages are discussed. Specific topics covered are as follows: Levels of abstraction C++ for digital design SystemC RT level and above TLM methodology TLM timing aspects TLM channels TLM channels Mixed level design NoC TLM modeling System testing