This course discusses faults and fault modeling, test equipment, test generation for combinational and sequential circuits, fault simulation, memory testing, design for testability, built-in self-test techniques, boundary scan, IEEE 1149.1, and board and SoC test standards. Various fault simulation and ATPG methods including concurrent fault simulation, D-algorithm, and PODEM are discussed. Controllability and observability methods such as SCOAP for testability analysis are discussed. Various full-scan and partial scan methods are described and modeled in Verilog and tested with Verilog testbenches. BIST architectures for processor testing, memory testing and general RT level hardware testing are described, modeled in Verilog and simulated and evaluated for fault coverage. The course uses Verilog testbenches for simulating golden models, developing and evaluating test sets, and for mimicking testers.
Prerequisites
Understanding digital systems and design of combinational and sequential circuits, Understanding a hardware description language (VHDL or Verilog) and the use of these languages for simulation and synthesis